Simultaneous Delay, Yield, and Total Power Optimization in Deep-submicron Cmos Technology Using Gate-sizing, Threshold Voltage Assignment, Nodal Control, and Technology Mapping

The aggressive scaling of CMOS technology below 90nm brings forth many great new physical challenges that must be addressed in the forefront of the design cycle. In addition to meeting the usual timing and dynamic/switching power budgets, designers must also now carefully consider issues such as leakage current/power, crosstalk noise, electromigration, IR drop, and even manufacturing process variations. This thesis explores several novel techniques for mitigating the effects of leakage current and process variations. In the first part of this thesis, a circuittuning method for simultaneous optimization of critical delay, dynamic power, leakage power, and yield will be proposed. The method is based on Generalized Lagrangian Relaxation, and involves gate-sizing and multiple threshold voltage assignment. Experimental results show that this method can not only effectively tune a circuit with over 15,000 variables and 8,000 constraints in under 7 minutes, but it can also minimize the impact of process variations on timing. In the second part of this thesis, a ROBDD-based nodal control technique called Sectoral Partial Vector Control (SPVC) will be proposed to address the minimization of CMOS subthreshold leakage current/power. Together with leakage-aware technology mapping, this method was empirically shown to be capable of reducing the total static leakage power consumption by as much as 69%. Overall, the two proposed techniques in this thesis can be used either independently or together to provide a comprehensive and effective circuit optimization framework for today’s complex designs.